1. Field of the Invention
The present invention relates to packaging of electronic devices. More particularly, the present invention relates to a sealing layer that protects the surface of a semiconductor die and is also used to form conductive bumps on the die bond pads.
2. State of the Art
Factors of cost and density are increasingly important in the electronics industry. Conventionally, high density electronic devices in the form of semiconductor dice are packaged in housings for protection from the environment and to provide electrical connections with the higher level circuit structures into which they are incorporated. In an effort to reduce size and expense, semiconductor manufacturers have developed chip scale package (CSP) structures which add minimal dimension to the completed devices and eliminate processing steps associated with prior packaging methods. These CSP structures often involve forming protective polymer layers or other material films adhered directly on a surface of a semiconductor die to seal it from the environment. According to this process, a passivation layer is typically formed on the active surface of the die with apertures to expose the die bond pads, and an under-bump metallization (UBM) layer is formed over the exposed bond pads. The UBM layer provides improved bonding properties and, if necessary, extends across the passivation layer in the form of a redistribution layer to relocate the external contact locations for connecting the die to higher level circuit structures. Discrete conductive elements in the shape of bumps or balls are then formed on or attached to the external contact locations to enable connection with higher level circuit structures by flip-chip or tape automated bonding (TAB) attachment. A mask layer may optionally be applied to surround the external contact locations prior to forming the conductive bumps, which prevents the bump material from wicking onto adjacent die surfaces. Finally, a layer of polymer or similar sealing material may be coated onto one or more surfaces of the die to complete the CSP. The completed package is essentially no larger than the die itself.
A further advantage of CSP structures is that they may be fashioned wholly or in part prior to the singulation of a wafer containing a plurality of semiconductor die locations. This approach, often being referred to as “wafer-level packaging,” thereby provides simultaneous formation of a large number of electronic device packages. After the desired circuitry, bond pads, a passivation layer, UBM and optional mask layers for the electronic devices have been fabricated on the active surface of the wafer, conductive bumps are provided using conventional formation methods. One widely used method is by evaporative deposition of metal onto a mask. The mask is formed on the wafer with apertures corresponding to the bond pad locations and consecutive layers of metal are deposited in the apertures. Once enough metal is deposited, the mask is removed and the metal is reflowed by heating to a molten state to form a final bump or ball shape. Another alternative is to employ stencil printing. Rather than evaporating metal through a mask, a solder paste is screened over a stencil and fills apertures therein corresponding to the bond pad locations. The stencil is removed from the surface of the wafer, and the solder is reflowed for bonding to the UBM. Once the conductive bumps are in place, the entire active surface of the wafer is coated with the aforementioned CSP sealing layer. This is accomplished by molding, spin-coating or otherwise applying the sealing layer to the surface of the wafer by methods known in the art. The wafer is subsequently singulated to excise the individual semiconductor dice, and further sealing layers may be added to coat any remaining exposed die surfaces.
A disadvantage to wafer-level packaging has been that the above-described methods for forming conductive bumps are often cumbersome and unreliable. The evaporative deposition method, for instance, requires a great deal of time to apply the metal and further involves a large capital investment for deposition equipment. Likewise, in the stencil printing method, portions of the solder paste may be retained in the stencil apertures during removal, thereby producing nonuniform bump volumes which create problems with die connection to higher level circuit structures. Stencils used for bump formation also typically require aperture depths of only a few thousandths of an inch and are, therefore, constructed of thin sheets of material which may be easily damaged during handling. Another drawback that has heretofore been encountered with wafer-level packaging involves forming the conductive bumps before applying the sealing layer to the wafer active surface. The sealing layer often completely covers the conductive bumps and must, therefore, be etched back, ground down or otherwise partially removed to expose the conductive bumps for electrical contact. Furthermore, surface tension between the sealing layer material and the conductive bumps can cause irregularities during coating and thereby reduce the uniformity of the sealing layer.
Prior to singulation of the semiconductor dice from the wafer, it may also be necessary to reduce the thickness of a wafer by back grinding. This is desirable to minimize the amount of time required to saw through a thick wafer during singulation and further reduces the final package size. Because back grinding is typically carried out after formation of the conductive bumps, it is necessary to cover them with a protective adhesive tape during the grinding operation. Further processing must then be carried out to remove the tape and clean the conductive bumps of any residual adhesive material.
Plainly, what is needed are CSP structures and wafer-level packaging methods that eliminate existing problems associated with forming and further processing conductive bumps on the active surface of semiconductor dice.